Arias Garcia, JanierMafra, Augusto AmaralGade, Liliane dos ReisCoelho, Frederico Gualberto FerreiraCastro, Cristiano Leite deTorres, Luiz Carlos BambirraBraga, Antônio de Pádua2022-09-152022-09-152020ARIAS GARCIA, J. et al. Enhancing performance of Gabriel graph-based classifiers by a hardware co-processor for embedded system applications. IEEE Transactions on Industrial Informatics, v. 17, p. 1186-1196, 2021. Disponível em: <https://ieeexplore.ieee.org/document/9072429>. Acesso em: 29 abr. 2022.1941-0050http://www.repositorio.ufop.br/jspui/handle/123456789/15312It is well known that there is an increasing interest in edge computing to reduce the distance between cloud and end devices, especially for Machine Learning (ML) methods. However, when related to latency-sensitive applications, little work can be found in ML literature on suitable embedded systems implementations. This paper presents new ways to implement the decision rule of a large margin classifier based on Gabriel graphs as well as an efficient implementation of this on an embedded system. The proposed approach uses the nearest neighbor method as the decision rule, and the implementation starts from an RTL pipeline architecture developed for binary large margin classifiers and proposes the integration in a hardware/software co-design. Results showed that the proposed approach was statistically similar to the classifier and had a speedup factor of up to 8x compared to the classifier executed in software, with performance suitable for ML latency-sensitive applications.en-USrestritoMachine learningSystem on a chipLarge marginLatency sensitiveIoTArtigo publicado em periodicohttps://ieeexplore.ieee.org/document/9072429https://doi.org/10.1109/TII.2020.2987329